Application of In-situ Pre-epi Clean Process for Next Generation Semiconductor Devices

Application of In-situ Pre-epi Clean Process for Next Generation Semiconductor Devices

As electronic devices are evolving to more diversified and specifically function-oriented applications, silicon-based semiconductors have shown their limitation to unprecedented functionality requirements such as high power, high frequency, and high temperature operation. Growing utilization of IV-IV compounds (e.g. SiGe, SiC), III-V compounds (e.g. GaAs, GaN) as well as hetero-epitaxial structures with Si has become an inevitable trend.

Advanced Chemical Concentration Control for Fabrication of Devices Using SiC

Advanced Chemical Concentration Control for Fabrication of Devices Using SiC

In conventional MEMS fabrication, relatively inert compounds such as Si3N4 are used as an etch stop or mask for creating patterns on wafers. However, materials such as this require insight as to their etch selectivity corresponding to that of the substrate material and are not suitable for high temperature devices.

Cost of ownership comparison of single wafer processes for stripping copper pillar bump photomasks

Cost of ownership comparison of single wafer processes for stripping copper pillar bump photomasks

A new generation of negative tone and chemically amplified positive tone photoresists by TOK, JSR, Dow Chemical and others has gained momentum for advanced packaging applications. Resist thickness requirements are increasing to the 40-100 μm range as Cu pillars and micro-bumps are adopted, to accommodate the tighter pitches required in the newest multi-chip package designs. In order to form the pillars, the resist mask must be thicker than the height of the pillars to contain the entire bump structure.