Using an Ozonated- DI-Water Technology for Photoresist Removal

Traditional wet cleaning processes rely on a mixture of sulfuric acid and hydrogen peroxide (SPM) or sulfuric acid with ozone (SOM). Although these chemicals are highly effective, the  operating costs for sulfuric-based processes are significant.7 Vast amounts of DI water are consumed to rinse off resid- ual sulfuric acid and unoxidized particulate matter from wafer and carrier sur- faces during the wet cleaning process, and expenses are incurred both in obtaining the water and treating and dis- posing of postprocess wastewater. Other operating costs include the expenses involved in the storage, distribution, and treatment of sulfuric acid mixtures and in the frequent replacement of wet station components. Such components have limited life spans because of their constant exposure to high process temperatures—generally >130°C—and the corrosive properties of the acid.

The use of a DIO ₃ cleaning tool, such as that developed by Akrion (Allentown, PA), can offer several advantages over other photoresist removal procedures. Its adoption can simplify the stripping process by replacing two separate steps—dry ashing and wet cleaning—with one, and reduce operating costs by eliminating expensive, and environ- mentally unfriendly, sulfur-containing process chemicals. While minimizing defect densities and organic residue, the technology may also offer a smaller footprint than methods that require multiple process baths.

The DIO₃ Process

Unlike the SPM process, in which resist is undercut, floats away, and then is oxidized by hydrogen peroxide, the DIO ₃ process directly oxidizes resist on the wafer surface. The resist becomes progressively thinner during this reaction, and the cleaning solution remains clear during the entire process. The chemical reaction that takes place during the DIO₃ process is

-CH2– + 3O3 ® 3O2 + CO2 + H2O

and the reactions in SPM processes are

H2SO4 + H2O ® H2SO5 + H2O

-CH2 +3H2SO5 ® 3H2SO4 +CO2 +H2O

Figure 1 depicts the two types of stripping procedures in simplified schematic drawings. In addition to directly oxidizing the resist, the oxidation reaction in DIO₃ processing between ozonated water and bare silicon induces the growth of a thin (~9.5-Å) oxide layer on the wafer surface. This chemically induced oxide minimizes particle additions be- cause both the zeta potential on the silicon surface and the Van der Waals attractive force between the wafer and particles are reduced when the previously hydrophobic sur- face is rendered hydrophilic. The oxidation reaction also minimizes levels of total organic compounds.

The flow scheme in the DIO₃ immersion equipment is shown in Figure 2. In this system, ozone is produced from O₂ gas in an ozone generator and fed into a static mixer, where it is combined with DI water. This mixture is then fed into the bottom of the process bath. Gaseous ozone is also fed in a uniform stream to the bottom of the process bath via a specially designed diffusion device. The gaseous and dissolved ozone enter the bath simultaneously, and both are monitored using in-line analysis. With closed-loop re- circulation, liquid flows from the process vessel to a pump, after which it flows through a heat exchanger, a sensor, and a filter back to the mixer. Finally it reenters the vessel. In this system, the dissolved ozone concentration stabilizes in the range of 10–50 ppm, depending on the process temperature (which can range from 18° to 50°C).

Process Optimization Studies

 

During the development of the DIO ₃ system, a variety of tests were conducted to assess the technology’s photoresist removal effectiveness.

Strip Rate. One set of tests assessed the effect of process temperature and ozone concentration on the average photoresist stripping rate. As the results in Figure 3 indicate, the stripping rate increased  dramatically with an increase in

the dissolved ozone concentration in the process bath. The data also show that the optimal baked-photoresist removal rate averaged 65 nm/min at ambient temperatures <40°C. This low- temperature capability great- ly simplified equipment design and maintenance by eliminating the need for an upstream heater or heat exchanger. Strip-rate tests were run using many types of photoresist in addition to that used to achieve the results shown in Figure 3. The resists tested included AZ 1518, 7209, and

7220; HIPR 512; JSR 7158 and IX710; MCPRi 7010; PFX

Figure1: Simplified schematics of the DIO₃ and SPM photoresist stripping processes. In 15D1;  PFI  26A,  26B,  and

DIO₃ cleaning, resist is oxidized directly, whereas inSPM procedures, it is first undercut 38A9; Shipley S1808 and

and then flows free of the wafer before oxidation.                                                                             S 1813; a nd Sy s t e m 827

THMR-ip 3300. It was found that the stripping rate does not depend on the resist type.

Although the removal rate achieved in this testing seems low compared to some previously published data from studies at sub-ambient temperatures, it should not be a concern in future device manufacturing processes.5 The photoresist thickness used in critical processes such as gate line,

deep and small metal contact, and shallow trench isolation is expected to remain below 500 nm for sub-quarter-micron IC devices.

Micro contamination. In implementing the DIO ₃ technology, the level of metal contaminants in the process bath was a major concern for several reasons. The process tool uses a metallic electrode to generate reactive ozone from

oxygen, and it is known that metallic impurities have a tendency to adhere to hydrophobic surfaces after photoresist stripping. Minute amounts of such impurities can cause various defects, including silicide/silicate formation, gate oxide integrity failure, silicon surface pitting, and electrical current leakage in dielectrics in front-end processes. To address this concern, the metallic contamination contribution of the DIO₃ process was evaluated using vapor-phase de- composition total reflection x-ray  fluorescence  spectroscopy (VPD-TXRF).

Figure3:Data showing the effect of process temperature and dissolved ozone concentration .

on the average stripping rate of the DIO₃ process with a baked 1.3-µm photoresist. The optimal removal rate averaged 65nm/min.

Comparative results for wafers processed by either DIO₃ or SPM are presented in Table I. As these data indicate, no significant metallic contamination was observed on wafers processed with DIO₃. In addition, sulfur contamination, a significant cause of wafer surface hazing associated with SPM processing, was not observed following the ozonated- water process. It is believed that DIO ₃ eliminates ionized metallic impurities from the wafer surface via the oxidation reaction of the highly reactive ozone radical (O₃+).

The stripping rate increased dramatically with an increase in the dissolved ozone concentration in the DIO₃ process bath.

In a typical manufacturing environment, the SPM photoresist stripping process sequence includes RCA standard cleans 1 and 2 (SC-1 and SC-2). The SC-2 clean, which consists of hydrochloric acid (HCl) and hydrogen peroxide,

is used to remove metallic residues such as iron and zinc, which are often deposited during the SC-1 step. With DIO ₃ processing, injecting a small amount of HCl into the process water or the postprocess rinse water effectively removes such trace metals from the wafer surface, eliminating the need for the SC-2 step and thereby lowering overall operating costs.

The possibility of eliminating the SC-1 step following the DIO₃ process was also investigated. In that study, sur- face particles ³0.16 µm were measured with a Surfscan 6200 (KLA-Tencor, San Jose). As shown in Table II, the final par- ticle counts following a DIO₃/SC-1/rinse/dry sequence were lower than those obtained following DIO ₃/rinse/dry or DIO₃/dry sequences. Compared to the DIO ₃/rinse/dry results, the counts were approximately 25% lower when the SC-1 step was included.

On certain highly implanted wafers, where the photoresist is used as a blocking layer to form a shallow junction (for source and drain) after gate etch, it is desirable to com- bine dry ash and wet chemical stripping processes. In such cases, SPM followed by SC-1 is the usual post-dry-ashing wafer cleaning sequence. The role of SPM is to remove by-products that are formed during the reaction between

photoresist and the reactive gas in the ashing chamber. To investigate the use of ozonated water rather than SPM in this postash cleaning step, light-point defect measurements were taken on wafers that had been treated using various process sequences. As shown in Figure 4, the DIO ₃-only treatment was not sufficient to obtain good defect counts; however, the combined DIO₃ and SC-1 process sequences yielded satisfactory to excellent results, particularly when a 20-minute DIO ₃ immersion was used.

The Recommended Process. Based on the studies dis- cussed above and assuming a common device structure of

<12,000 Å, the recommended process sequence for photoresist removal with DIO₃ is as follows:

1. A 15–20-minute immersion in the DIO ₃ process bath at ambient temperature to remove
2. SC-1 processing for 7–10 minutes at 50°C with mega- sonics to remove particles and light
3. A 7–10-minute cascade-type DI rinse at ambient temperature to rinse off the SC-1 chemistry and cool the wafers
4. An 8.5-minute cycle in a dryer to remove rinsewater from the wafers.

  

Figure4:Light–pointdefect(LPD)measurementsindicatingtheefficiencyofDIO₃aloneand combined DIO₃andSC-1processesforpost-dry-ashingwafercleaning.

As the m icrog raphs i n F i g ur e 5 i nd ica t e, th i s DIO ₃/SC- 1 /rinse/dry sequence thoroughly removes the photoresist from a patterned wafer. (Before under- going the DIO₃ process, the wafer shown had a 1.05-µm- thick HipR 6512 resist layer hard baked at 100°C.)

Electrical Performance and Yield

 

In another study (the results of which are presented in Figure 6), researchers investigated the effect of DIO₃ processing on device properties and yield.8 In that work, the intrinsic breakdown of thin oxide on simple gate modules was measured on wafers cleaned with either a DIO ₃ or SPM process followed by standard cleans SC-1 and SC-2. The gate oxide layer was 120 Å thick. These measurements indicated that the probability of intrinsic QBD failure—which may result from defects caused by such contaminants as particles, organic residue, and metallic impurities—did not differ significantly for wafers cleaned with the two processes. Yield loss for wafers processed using DIO₃ was also comparable to that for wafers cleaned with SPM.

Conclusion

 

Studies have shown that DIO ₃ is a viable substitute for sulfuric acid mixtures in semiconductor resist stripping processes. When followed by an SC-1 clean, DIO₃ processing minimizes metallic contamination and particle addition on the wafer surface. The technology is also environmentally friendly and reduces operating costs be- cause it eliminates the use of corrosive chemicals. More importantly, neither electrical device characteristics nor overall production yields are negatively affected by using the DIO₃ process.

Acknowledgments

 

The authors wish to thank

Figure5:Micrographs (100´) ofapatternedwaferbefore (a) andafter (b) DIO3 processing, Rene Vroom of Phillips Semi-

showingthatphotoresisthadbeenremovedeffectively.                                                             conductor and Stefan De Gendt

PROCESS SYSTEM	COUNT	AT 50% (arbitrary) units)	BELOW 4.500 (arbitrary units)
EQUIPMENTA (DIO3)	28	4.988	0.0%
EQUIPMENTB (DIO3)	30	5.019	0.0%
EQUIPMENTC (DIO3)	30	5.009	3.3%
SPM (WETBENCH)	35	4.948	5.7%

Figure6:Cumulativefailureofintrinsictotalchargeto breakdown.

Jae-InhSong,PhD,is vice pres- ident of process applications at Akrion in Allentown, PA. Be- fore assuming this position, he served as manager of the clean- ing and CMP process development team at Samsung’s semi- conductor R&D center. Song’s main interests include manufacturing-oriented surface preparation and characterization technology, and yield enhancement via implementation of cleaning technology. He has authored or coauthored more than 30 journal publications and 40 conference presentations. He is also the holder or coholder of approximately 100 semiconductor process a nd e q u i pm e nt – related patents. He received a

of IMEC for sharing valuable information regarding the effects of DIO₃ processes on electrical properties and device yields.

References

 

1. F Tardif et al., “Diluted Dynamic Clean: DDC,” in Proceedings of the Third International Symposium on Ultra-Clean Processing of Silicon Surfaces (Leuven, Belgium: ACCO, 1996).
2. F De Smedt et , “The Ozone Solubility and Its Decay in Aqueous Solutions: Crucial Issues in Ozonated Chemistries for Semi- conductor Cleaning,” in Proceedings of the Fifth International Symposium on Ultra-Clean Processing of Silicon Surfaces(Leuven, Belgium: ACCO, 2000), 143–144.
3. P Mertens and M Heyns, “A Controlled Deposition of Organic Contamination and the Removal with Ozone-Based Cleaning,” in Proceedings of the Fifth International Symposium on Ultra- Clean Processing of Silicon Surfaces(Leuven, Belgium: ACCO, 2000), 149–150.
4. I Kashkoush et , “An Alternative to Conventional Post-Ash Resist Stripping,” Future Fab International 1, no. 3 (1997), 249–253.
5. R Matthews, “A New Aqueous-Based Technology Employing Subambient Temperature Deionized Water and O₃ for Removing Organics,” in Proceedings of the Semiconductor Pure Water and Chemicals Conference (Sunnyvale, CA: SPWCC, 1998), 359–373.
6. K Christenson et al., “Cleaning Technology in Semiconductor Device Manufacturing III,” in Proceedings of the Electrochemical Society Conference (Pennington, NJ: The Electrochemical So- ciety, 1999).
7. W Kern, , Handbook of Semiconductor Wafer Cleaning Technology (Park Ridge, NJ: Noyes Publications, 1993).
8. R Vroom and S De Gendt, “The Use of Ozonated Water as Re- sist Strip and Post Ash Clean in a Production Fab,” in Proceed- ings of the IEEE International Symposium on Semiconductor Manufacturing (Piscataway, NJ: Institute of Electrical and Elec- tronics Engineers, 1999), 165–168.

PhD in solution chemistry in 1989 from the University of Glasgow, UK. (Song can be reached at 610/530-3607 or jaeinh@compuserve.com.)

Richard Novak, PhD,is vice president of advanced tech- nology and chief technical officer at Akrion. He previ- ously served as a member of the technical staff at RCA Laboratories and has more than 25 years of experience in the semiconductor industry. He also cochaired the first four International Symposia on Wafer Cleaning. Novak received his PhD in ceramic engineering from the University of Illinois (Champaign-Urbana) in 1972. (Novak can be reached at 610/530-3449 or richnovak @aol.com.)

IsmailKashkoush, PhD,is director of applications and pro- cess engineering at Akrion, where he is responsible for pro- cess R&D in the company’s Class 1 applications laboratory. Specializing in microcontamination characterization, re- moval, and control, Kashkoush has published more than 50 articles in the area of wafer surface preparation. He received his PhD in engineering sciences from Clarkson University (Potsdam, NY) in 1993. (Kashkoush can be reached at 610/530-3379 or kashkoush@aol.com.)

Pieter Boelenis manager of European process support and applications for Akrion in Grenoble, France. He is respon- sible for a process research project at the Laboratory of Elec- tronics, Technology, and Instrumentation (LETI) and cus- tomer application support in Europe. Boelen has authored or coauthored several publications in the area of wafer clean- ing and surface preparation. He holds a degree in electron- ics engineering. (Boelen can be reached at +33 4 76884006 or pieter_boelen@compuserve.com.)

Reprinted from MICRO, January 2001 • Copyright ã 2001 Canon Communications LLC